CR85
11/22/2021, 7:31 AMMatthew Guthaus
11/22/2021, 2:47 PMCR85
11/22/2021, 6:34 PMCR85
11/24/2021, 8:33 AM*****
***** Welcome to the Xyce(TM) Parallel Electronic Simulator
*****
***** This is version Xyce Release 7.4-opensource
***** Date: Wed Nov 24 00:32:11 PST 2021
***** Executing netlist gmId.netlist
***** Reading and parsing netlist...
Netlist warning in file
/home/chandru/Tools/open_pdks/sky130/sky130A/libs.tech/ngspice/all.spice at
or near line 2
Unrecognized dot line will be ignored
Netlist error in file
/home/chandru/Tools/open_pdks/sky130/sky130A/libs.ref/sky130_fd_pr/spice/sky130_fd_pr__nfet_01v8__tt.pm3.spice
at or near line 31
Model is required for device MSKY130_FD_PR__NFET_01V8 and no valid model card
found.
Simulation aborted due to error. There are 0 MSG_FATAL errors and 1 MSG_ERROR
errors
*** Xyce Abort ***
CR85
11/24/2021, 8:35 AMNetlist
.options nonlin continuation=gmin
.options timeint method=trap
.options device temp=25
.options output initial_interval=1e-8
*.options parser model_binning=true
* Model Includes and Std Cell Includes
.param mc_mm_switch=0
.param mc_pr_switch=0
.lib ../../../Tools/open_pdks/sky130/sky130A/libs.tech/ngspice/sky130.lib.spice tt
.options nonlin continuation=gmin
.options timeint method=trap
.options device temp=25
.options output initial_interval=1e-8
.param kw = 1
.param pvdd = 1.8
* --- Voltage Sources ---
vdd supply 0 dc 'pvdd'
vsig vi 0 dc 'pvdd'
** Change W to tfin need to verify
* --- Inverter Subcircuit ---
XM1 supply vi 0 0 sky130_fd_pr__nfet_01v8 L=0.15 W=1
*MM0 supply vi 0 0 nmos_slvt tfin=6.5n l=7n nfin='kw'
*Idd supply drn0 dc 1m
*Rg vi drn0 1m
*Xinv1 vi 1 supply 0 mg_inv
*Xinv2 1 2 supply 0 mg_inv
*Xinv3 2 3 supply 0 mg_inv
*Xinv4 3 4 supply 0 mg_inv
*Xinv5 4 vo supply 0 mg_inv
* --- Transient Analysis ---
*.tran 10n 5u
*.DC vsig 0 1 0.1
.DC kw 1 20 1
*.DC Idd 0 100e-3 0.05e-3
*.print dc v(drn0)
.op
.print dc {N(XM1:GDS)*N(XM1:GM)}
.print dc N(XM1:VTH)
.print dc N(XM1:IDS)
.print dc N(XM1:VDSSAT)
.print dc N(XM1:VGS)
.print dc N(XM1:VDS)
.print dc N(XM1:GDS)
.print dc kw
.print dc N(XM1:CGG)
*.print tran {v(vi)+1} {v(vo)+1}
*comp {v(vi)+1} reltol=1e-2
*comp {v(vo)+1} reltol=1e-2 abstol=1e-5 zerotol=1e-8
.end
Matthew Guthaus
11/24/2021, 11:52 AMMatthew Guthaus
11/24/2021, 11:55 AMMatthew Guthaus
11/24/2021, 11:55 AMCR85
11/24/2021, 6:10 PM*****
***** Welcome to the Xyce(TM) Parallel Electronic Simulator
*****
***** This is version Xyce DEVELOPMENT-202111241005-(Public_Release-7.3.0-373-g82a079af)-opensource
***** Date: Wed Nov 24 10:08:34 PST 2021
***** Executing netlist gmId.netlist
***** Reading and parsing netlist...
Netlist error: Cannot convert 'x' to double for expression SCALE
Netlist error in file gmId.netlist at or near line 28
Model is required for device M1 and no valid model card found.
Simulation aborted due to error. There are 0 MSG_FATAL errors and 2 MSG_ERROR
errors
*** Xyce Abort ***
CR85
11/24/2021, 6:10 PMCR85
11/24/2021, 6:10 PMCR85
11/24/2021, 6:18 PMMatthew Guthaus
11/24/2021, 6:45 PMMatthew Guthaus
11/24/2021, 6:45 PMCR85
11/24/2021, 7:08 PMCR85
11/24/2021, 7:11 PMCR85
11/24/2021, 7:14 PMCR85
11/24/2021, 7:18 PMCR85
11/24/2021, 7:19 PMCR85
11/24/2021, 7:23 PMMatthew Guthaus
11/24/2021, 7:46 PMCR85
11/24/2021, 8:07 PMEric Keiter
01/03/2022, 6:44 PMEric Keiter
01/03/2022, 6:46 PM.options parser scale
but the most recent versions have been adapted to also support the more standard .option scale
. Note that for this more standard syntax the word option
is not plural.Eric Keiter
01/03/2022, 6:51 PM.param foo=1.0e-6
.option scale=foo
.step foo list 1.0e-6 2.0e-6 3.0e-6
then Xyce would run the circuit 3 times, with a different value of foo
each time. But, since (currently) the value for scale is only applied during parsing, it would not properly update the value on the 2nd and 3rd .STEP
iterations.Eric Keiter
01/03/2022, 6:56 PM.STEP
problem I just mentioned. But outside of that issue, it would not be hard to make that change in the parser.Eric Keiter
01/03/2022, 6:58 PMN()
output, that has been our .PRINT
line syntax for outputting internal device variables including (sometimes) device parameters. Currently, it doesn’t support as many internal device variables as we’d like it to. So, depending on what you are trying to output you might run into limitations. But it looks like it is working for you. It can be tricky to use for devices that are deep inside of subcircuit hierarchies, as you have to fully resolve the name.