<@U01L8BR7FFA> thanks! What was the issue you ment...
# fpgar
Rob Taylor
03/30/2021, 12:23 PM@User thanks! What was the issue you mentioned you were having?
n
Nguyen Dao
03/30/2021, 1:25 PMstill stuck at STA run and don’t know why set_disable_timing (sdc constraints) couldn’t get the cell’s pins in the gate netlist, e.g.,
…
Warning: fabric4.sdc, 445 pin ‘Tile_X4Y4_LUT4AB/Inst_LUT4AB_switch_matrix/J_l_GH_BEG*’ not found
…
r
Rob Taylor
03/30/2021, 2:36 PM@Tim 'mithro' Ansell any ideas who could help?
Rob Taylor
03/30/2021, 11:25 PM@Nguyen Dao see tim’s reply out of thread -ask on #openlane
n
Nguyen Dao
03/31/2021, 10:02 AMThanks @Rob Taylor and @Tim 'mithro' Ansell, that issue is not because of openSTA. The flow uses OpenPhySyn for Timing Optimization (psn) and this one doesn’t support all STA commands (e.g. get_pins).
r
Rob Taylor
03/31/2021, 10:03 AM@Nguyen Dao cool. Do raise your issue on #openlane
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Nguyen Dao
03/31/2021, 10:07 AM@Rob Taylor any ideas why routing takes so long just for a small fabric (4x4 CLBs only)? It’s still running after 12 hrs?
(1 single CLB only took 8 mins)