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<@U01L8BR7FFA> did `make timing`  in the sky water pdk root fix it for you?

I can apply patch in the skywater-pdk but the openlane uses different lib files in PDK_ROOT sky130A/libs.ref/sky130_fd_sc_hd/lib when setting up the openlane from this <https://openlane.readthedocs.io/en/latest/index.html#flow-configuration>

Does it work if I replace those lib files from PDK_ROOT by fixed ones in skywater-pdk?
Sorry, still not clear as there’re different directories between skywater-pdk and PDK_ROOT (openlane)

PDK_ROOT is an environment variable that you set to point to the skywater-pdk 

What you need to do is just go into the skywater-pdk directory and run `make timings`

That should be the same directory as you set PDK_ROOT to when you run openlane make

<@U01L8BR7FFA>If you want we can screenshare later and I can help you through it

Failing that, try this - <https://github.com/google/skywater-pdk/files/6251392/sky130_fd_sc_hd__tt_025C_1v80.zip>

sky130_fd_sc_hd_LIBvsLEF.png

Thanks <@U01GE4F371D>. I did manually modified the lib file to match with pin/layer descriptions in the LEF file (attached) but seems we have a issue with power connections/pins:
…
connect(2): no such node Tile_X1Y1_LUT4AB/Inst_LUT4AB_switch_matrix/_4334_/VNB
connect(1): no such node Tile_X1Y1_LUT4AB/Inst_LUT4AB_ConfigMem/Inst_frame13_bit1/_1_/VGND
…
WARNING: missing bias (6) /Tile_X1Y2_LUT4AB/Inst_LUT4AB_switch_matrix/_2347_/VNB at (sky130_fd_sc_hd__a32o_4)/MMNA0
WARNING: missing bias (6) /Tile_X1Y2_LUT4AB/Inst_LUT4AB_switch_matrix/_2347_/VPB at (sky130_fd_sc_hd__a32o_4)/MMPA0
….
Those can be reproduced from fabric22 on <https://github.com/FPGA-Research-Manchester/FABulous-SKY130>

it’s not just swapping “related_bias_pin” VNB/VPB but also the pg_type/layer pwell (VNB) and nwell (VPB) too

You can probably figure how to do that using the script, but if not I’ll be able to have a try at it late tonight

<@U01L8BR7FFA> ok, i had a try at this. fix is in bug 288