Could someone explain how the OSU decap cells work? More specifically how this structure is better than the others? The first image is of some typical layouts I found on the internet. The second is of the OSU 12 track decap cell. The best reasoning that I can come up with the for this structure is to minimize nmos leakage while staying ESD resistant (compared to NMOS/PMOS/NMOS+PMOS). Third image is of a decap cell from the HD library. It looks like the standard NMOS+PMOS decap cell.

The OSU one is interesting because it doesn't use the gate dielectric for the decap like the other standard decaps. This is typically the highest density since it is so thin. Instead, it seems to be using the source/drain caps which are less dense but still significant. I'm not sure the advantage though .. it is thinner, so it's easier to fit in places?

Oh yes it would be thinner. Hadn't considered that 😅. Thank you!