DRC violations are down to zero, and I've been trying to understand if this LVS issue is a problem or not:

LVS Summary:
Source: /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/lvs/user_project_wrapper.lvs_parsed.lef.log
    net count difference = 0
    unmatched nets = 0
Total errors = 1

The only issue I can see is one pin appears twice:

io_oeb[27]                                 |io_oeb[27]
io_oeb[27]                                 |(no matching pin)
...
Cell pin lists for user_project_wrapper and user_project_wrapper altered to match.
The top level cell failed pin matching.

@Anton Blanchard: Is there 2 pin definitions for io_oeb[27] in the DEF, spice or powered verilog? Otherwise, Sometimes netgen (reportedly) makes that confusion with OpenPhySyn buffer insertion (so sometimes it's a false error, you'll need to track it down), but since this is the top level, you could just rerun it with:

set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0

And see if the LVS error is gone. Maybe, @Ahmed Ghazy can shed more light on this if he'd faced it before.

I haven't run into this specific instance of the error, where a pin appears twice on the layout side. I highly doubt it appears twice in the DEF, but I would start t here as Amr suggested.

The DEF pin definition has:

- io_oeb[27] + NET psn_net_177 + DIRECTION OUTPUT + USE SIGNAL + PLACED ( -1200 2405500 ) N + LAYER met3 ( -3600 -600 ) ( 3600 600 ) ;