booted caravel, selected one design out of several, configured the gpios as clock and reset in, 7 segments out, then used wishbone to update compare register, logic analyser to reset and finally watched the 7 segments count up to 9! This took about 3 days!

what software did you use to do the simulation?

I copied the makefile for the user project testbench here: https://github.com/efabless/caravel/blob/release/verilog/dv/caravel/user_proj_example/io_ports/Makefile