How are people planning to implement their designs into caravel? * Are you directly adding sources to user_project_wrapper.config, keeping the DIE_AREA + pins etc. the same as required (I think this recommended in the videos) * Are you doing something similar to user_proj_example, making the GDS/LEF out of that, then adding your top level verilog as a blackbox treating? I don't have a design that needs the entire user project area and doing the former has an extremely long runtime. I've not tried much with the latter approach yet but if there is a runtime benefit that would be great

Yeah, I'll do it exactly like user_proj_example with the top level wrapper.

yes it does seem to make it much, much worse.. https://github.com/efabless/openlane/blob/develop/doc/hardening_macros.md#power-grid-pdn It looks like every component except the top level would be a macro (which is caravel, which we shouldn't be concerend with?) but the config.tcl examples don't use

DESIGN_IS_CORE = 0

, such as DFFRAM and mgmt_core, what part am I missing here?

I am also planning to put

my_soc

as the blackbox in the wrapper. The caravel should then just be placing and routing between them.

@drr No, don't pay attention to that. you want to synthesize your top level normally and have it generate all the power grid. The wrapper will really just take care of routing to the pins.

@tnt is the config.tcl you have in both the wrapper and wrapped module pretty much the same as the default caravel ones, except for the die area on your user project?

huh no, the one for my project is significantly different

this one right? https://github.com/PyFive-RISC-V/pyfive_no2usb/blob/master/config.tcl

No, that's for an internal macro.

right