I am trying out the develop branches of caravel and openlane (uses the latest skywater and one of the latest _open_pdks_) from this morning. Seems that caravel Makefile is still missing the main make target. The default user_project_wrapper runs OK, as well as with a small design incorporated. Things get complicated and error-prone after specifying a more complicated design. Also, the latest openlane still uses openroad version with the

write_verilog -include_pwr_gnd

command issue from above (cannot use

PL_OPENPHYSYN_OPTIMIZATIONS

).

@Dejan Petkovic: caravel chip completion (+ makefile) is still a WIP. However, if you're using openlane:develop then you need to set the IMAGE_NAME to openlane:rc5 (you'll find it set to rc4 in the makefile; you can simply export it tho). There is no

write_verilog -include_pwr_gnd

issue, you're just using an rc4 docker with rc5 code.

Yes, thanks. So, IMAGE_NAME needs to be changed in caravel:develop/openlane/Makefile, too. I'm now getting a

child killed: segmentation violation

during timing optimization. I 'll keep on debugging...

@Dejan Petkovic: it might be a RAM issue, try increasing the target

::env(CLOCK_PERIOD)

I went up to 1000 (1MHz), it's definitely not because of that. Thanks.