In caravel, how would a wishbone slave component assert an interrupt to the management core?

AFAIK, there's no internal interrupt mechanism

Don't suppose that's something the logic analyzer lines can be configured to 😛

I don't believe so, unless it was added recently?

Yuck, perhaps drive an external pin that can be looped back to the external IRQ port? Odd that an internal interrupt line for internal peripherals wasn't included.

if you're polling on LA lines at some point you're better off just polling the component over wishbone But yeah I'd design for a loopback where you jumper an output GPIO to the irq pin, and maybe have a make target that enables a not-strictly-caravel-harness build where they're tied together in GDSII instead (and possibly go further routing from the user area directly into a separate IRQ channel, but presumably flexibility around "must use Caravel test harness" is extremely finite)

The rigid user project constraints make sense in order to yield the best possible 1st spin success rate. However, support for internally generated interrupts seems like a pretty basic SOC requirement. Opened a ticket at the repo... we'll see how that goes?