I'm trying to determine the ranges of user_clock2 to the user space. From the caravel datasheet, I see that the PLL trim explains a frequency range of 90-215MHz and then the PLL output divider (2) can pass through an undivided PLL clock or divide the PLL clock by values ranging from 2 to 7. In other words, if the PLL clock is 90MHz, then user_clock2 could be configured to be as fast as 90MHz or as slow as 12MHz (i.e., 90MHz / 7). Am I understanding this correctly?