@User The following is valid config for dual clocks.

set ::env(CLOCK_PORT) "wb_clk_i user_clock2"
set ::env(CLOCK_NET) "wb_clk_i user_clock2"

[INFO]: Performing clock tree synthesis...
[INFO]: Looking for the following net(s): wb_clk_i user_clock2

Thanks @Jean. I had asked about trying to do STA on multiple clocks in the openlane channel and this may be the syntax I need. Do you know if the SDC file is used at all?

👍

Haven't figured out where the .sdc file would plug in. I need to indicate that the clocks are asynchronous

@Jean, @tnt, @Matt Aamold: you can create a custom sdc file and include in the design directory then point to it in the config.tcl file of your design using:

set ::env(BASE_SDC_FILE) $(DESIGN_DIR)/the_name_of_the_file.sdc

Is this what you're looking for?

@Amr Gouhar Ok, this helps. Can you confirm that multiple clocks can be listed like @Jean showed at the start of this thread?

Yes,

CLOCK_NET

is used for CTS mainly (if it's undefined, we use the value given to

CLOCK_PORT

instead, so if they both have the same value no need to have

CLOCK_NET

defined). However,

CLOCK_PORT

is mainly used for STA and when sourcing the base.sdc file. We did this to allow STA and CTS to run on different sets of clocks. One use case would be if you don't want to do Clock tree synthesis by the flow for a specific net/clock port, however, you still want to include it when calculating the tns and wns of the design.

Thanks for that. As expected with two asynchronous clocks I am getting a lot of timing violations. Needed

set_clock_groups -asynchronous \
   -group [get_clocks {wb_clk_i}] \
	-group [get_clocks {user_clock2}]

@Jean where did you plug that ? Is there an option for custom sdc ?

Doesn't look like, but you can replace the base SDC with

set ::env(BASE_SDC_FILE)