tnt
12/06/2020, 11:02 AMyosys
ended up OOM'd when rewriting the verilog. 😕tnt
12/06/2020, 1:17 PMJean
12/07/2020, 1:08 AMtnt
12/07/2020, 8:27 AMset script_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) user_project_example
set ::env(VERILOG_FILES) "\
$script_dir/../../verilog/rtl/defines.v \
$script_dir/../../verilog/rtl/user_proj_example.v"
set ::env(BASE_SDC_FILE) \
"$script_dir/../../verilog/rtl/user_proj_example.sdc"
set ::env(CLOCK_PORT) "wb_clk_i"
set ::env(CLOCK_NET) "wb_clk_i user_clock2"
set ::env(CLOCK_PERIOD) "20"
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 2900 3500"
set ::env(DESIGN_IS_CORE) 0
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
set ::env(PL_TARGET_DENSITY) 0.30
set ::env(DIODE_INSERTION_STRATEGY) 0
# Need to fix a FastRoute bug for this to work, but it's good
# for a sense of "isolation"
set ::env(MAGIC_ZEROIZE_ORIGIN) 0
set ::env(ROUTING_CORES) 8
tnt
12/07/2020, 8:28 AMJean
12/07/2020, 3:55 PMtnt
12/07/2020, 3:58 PMtnt
12/07/2020, 3:58 PMJean
12/07/2020, 6:55 PMJean
12/07/2020, 6:58 PMABC: Node 20729 has dup fanin 20728.
ABC: Node 20731 has dup fanin 19943.
ABC: Node 20731 has dup fanin 20730.
ABC: Node 20731 has dup fanin 19943.
ABC: Node 20731 has dup fanin 20730.
ABC: Node 20733 has dup fanin 19953.