Though I wasn't able to regenerate `user_proj_example.gds`and

user_project_wrapper.gds

in the latest version of Caravel (due to not downloading openlane:rc6) I have now tried

make ship

and got a reasonable looking `caravel.gds`despite an error about 'Error while reading cell "control_logic_r" (byte position 5901488): Warning: Cell control_logic_r boundary was redefined.'. But looking at the result I was unable to see where the power rings in user_project_wrapper connect to the power in the overall chip. So I took another look at caravel_pyfive and it looks the same. What am I missing? How does the user project get power?