@User Is there a reason why ``default_nettype none` was set on some modules, while their port types are not explicitly defined?

no. the port types should also be defined. I felt the default_nettype was the most dangerous so I tried fixing that but it actually introduced a lot of issues.

I don't know, but is it not just regular Verilog 1995 port declaration to use implicit types? But I see why it might be unsafe. I wonder why iverilog is not complaining about it. I tested two other simulators, both printing errors.