Hi all, have anyone tried implementing JTAG for an...
# caravelt
Tayyeb Mahmood
05/29/2021, 10:19 AMHi all, have anyone tried implementing JTAG for any purpose in user area. I gathered that the board will have an FDTI link?
t
Tim Edwards
05/29/2021, 2:33 PMThe board will have an FTDI chip, but probably only single channel. Check #caravel-board and provide your own feedback to make sure that the board can accommodate this.
t
Tayyeb Mahmood
05/29/2021, 2:56 PMI actually posted the same there, but from caravel/verilog/rtl/Readme line 57, mprj_io[0] is for JTAG I/O.
Tayyeb Mahmood
05/29/2021, 2:57 PMNow, I wonder why only one pin is allocated for JTAG.
t
Tim Edwards
05/29/2021, 3:00 PMThat is reserved for the management SoC JTAG, but since the management SoC has not yet been synthesized with DFT support, it is not connected to anything. We have a version of the caravel management SoC with DFT as a project that taped out on MPW-one. Once that gets manufactured, tested, and validated, we'll incorporate the DFT into the management SoC for MPW-three.