HI, I have a question. I just realized that in my project synthesis is not optimizing out the unused top level pins. Is this expected ? Is there a don't touch command given on the top level pins somewhere ? Is it because we want the top level pins to be there so it is pin-compatible with the testing socket, if it has fewer pins, it may not be pin-compatible with the testing socket anymore ? Thanks

I would say it's expected. I have more experience with FPGAs, but even there I have never seen top level pins optimised away