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Is there any documentation other than the Verilog and the dv directory about how to set the wb slave ports on the wrapper? In example wb_poprt.c I can only tell it writes
``` reg_mprj_slave = 0x00002710;```


Hi, I use this video from <@U0172QZ342D> to understand how the wishbone works in contex of caravel.
<https://www.youtube.com/watch?v=jEQnLxADgr0&amp;ab_channel=ZeroToASICCourseZeroToASICCourse>

also you can check my wb_test in my repo <https://github.com/jaquerinte/caravel_radiation_harden>. The wb_test2 has an example of writting and reading from the wishbone bus .<https://github.com/jaquerinte/caravel_radiation_harden/blob/main/verilog/dv/wb_test2/wb_test2.c>

One thing missing from my video is that all over addresses must start with 0x30

<@U0172QZ342D> but also is possible to use more addresses that the ones that start with  0x30? in the manual I see that for the wishbone you can use from 0x30 to 0x7F, no?

No, the 0x30 is the part that tells the wb interconnect where to route the cycle and strobe. If it's not 0x30 you won't get those signals

Good idea to parameterise register addresses, makes the design more reusable

Thanks, but that was a side effect, because I need to duplicate one module and in-order to not duplicate code I make it parametric.