Is there a criteria for the /dv tests to pass other than console output? In our case

wait(mprj_io = ...)

is not exactly doable since we stream out multiple bits which could be 0/1. For some reason, it won't accept our custom assert which works fine in other test benches.

The dv/ tests use mprj_io because it's the most robust---least likely to break when we update the caravel design. However, you can also trigger off of an internal signal; the internal signal just needs a hierarchical name with all of the instance names of the verilog modules down to that signal.