Did any one implemented Caravel Harness in FPGA (replacing ASIC Tech macros like RAM , PLL etc with that of FPGA equivalent) . Just want to do Pre-silicon Validation and SW development for my design ?

I was interested in doing this as well

Planning to Port it to Arty A7-100T (https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board/) . So that the additional circuits for the Custom User Project design can be included as a Arduino shield (if required)

We have a few from my course, one targetting icebreaker. I'll post links later

I personally wanted to go after the ECP5 lattice dev board. I believe it supports shields as well. But if we architect the repo well we can support multiple targets and provide the option of the user space being in the same device or connected via shield. Thoughts?