< U01680FK487> Currently the `storage` macro in develop bran open-source-silicon.dev #caravel

<@U01680FK487> Currently, the `storage` macro in d...

Mitch Bailey

07/07/2021, 8:43 AM

@User Currently, the

storage

macro in develop branch of the caravel repo uses the

sram_1rw1r_32_256_8_sky130

macro. I'm hearing that maybe this is outdated. Are there plans to switch to the

sky130_sram_

prefixed versions? https://skywater-pdk.slack.com/archives/C017UA7LEUV/p1625586099026000

Manar Abdelatty

07/07/2021, 10:43 AM

@Mitch Bailey For mpw-two, we decided to go with the same macro used in mpw-one. I think the plan is to use the new model in mpw-three

Mitch Bailey

07/07/2021, 11:29 AM

@Manar Abdelatty Thanks for the heads up. I'm still trying to get LVS to pass. Looks like 32 power nets are not being recognized in each sram instance. I'll continue to look into it. I've completed LVS for the following blocks:

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gpio_control_block    (pin name mismatch)
mgmt_core             (spice models don't match)
mgmt_protect          (level shifter spice is incorrect)
user_id_programming

I'm working on these:

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chip_io
storage

And can't find the gate level verilog for

simple_por

. The

chip_io

appears to be missing the spice definitions for the following subcircuits. I couldn't find them in any of the spice libraries.

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sky130_fd_io__top_gpiov2
sky130_fd_io__top_power_lvc_wpad
sky130_fd_io__top_power_hvc_wpadv2
sky130_fd_io__top_ground_hvc_wpad
sky130_fd_io__top_ground_lvc_wpad

Manar Abdelatty

07/07/2021, 11:58 AM

@Mitch Bailey ( @Tim Edwards) I am seeing the same issue with the gpio_control_block. I think it is because magic is shorting the two grounds together and calls them

vssd1

, but from the verilog side it is called

vssd

so we end up with a pin mismatch between the two. But, I can't explain why the issue happens in the gpio_control_block and not other blocks where the grounds are shorted as well like mgmt_protect/mgmt_protect_hv. I am getting lvs clean with the mgmt_core with netgen, which spice models aren't matching ? For the simple_por, Tim E designed it in spice, so there is no gate-level and the golden reference should be the simulated spice netlist (https://github.com/efabless/caravel/blob/develop/subcells/simple_por/ngspice/simple_por.spice) The spice models for those should be defined here https://github.com/RTimothyEdwards/open_pdks/blob/master/sky130/custom/sky130_fd_io/spice/sky130_fd_io.spice . If you have the pdk installed, this file should be under

libs.ref/sky130_fd_io/spice

Matthew Guthaus

07/07/2021, 12:38 PM

@Manar Abdelatty that's to bad. That one lacks a dnwell isolation so it definitely has some issues... Why was that decided?

Tim Edwards

07/07/2021, 12:42 PM

I have a feature that has been in "beta test" mode for a while in magic; you can paint a ring of type "isosub" around one of the ground domains and it will extract as a separate net.

Tim Edwards

07/07/2021, 1:09 PM

I got

gpio_control_block

LVS clean by doing the following: (1) Remove the "assign vssd1 = vssd;" line from the gate level verilog. (2) Draw the "isosub" layer under the entire "gpio_logic_high" cell inside gpio_logic_high. (3) Draw the "isosub" layer under the entire "gpio_logic_high" cell inside gpio_control_block. The same method should be able to be applied to any block that has multiple ground domains.

Manar Abdelatty

07/07/2021, 1:15 PM

@Matthew Guthaus There was no particular good reason other than it was used in mpw-one, do you think the dnwell isolation issue is pressing to update it ?

Mitch Bailey

07/07/2021, 1:16 PM

@Manar Abdelatty Are you doing cell level LVS or device level LVS? If all your standard library cells are black boxes, you may not see the model differences. example 1 spice library

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.subckt sky130_fd_sc_hd__conb_1 VGND VNB VPB VPWR HI LO
X0 VGND LO VNB short w=480000u l=45000u
X1 HI VPWR VNB short w=480000u l=45000u
.ends

extracted

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.subckt sky130_fd_sc_hd__conb_1 VGND VNB VPB VPWR HI LO
R0 HI VPWR sky130_fd_pr__res_generic_po w=480000u l=45000u
R1 VGND LO sky130_fd_pr__res_generic_po w=480000u l=45000u
.ends

example 2 spice library

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.subckt sky130_fd_sc_hd__diode_2 DIODE VGND VNB VPB VPWR
X0 VNB DIODE sky130_fd_pr__diode_pw2nd p=5.36e+06u a=4.347e+11p
.ends

extracted

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.subckt sky130_fd_sc_hd__diode_2 DIODE VGND VNB VPB VPWR
X0 VNB DIODE sky130_fd_pr__diode_pw2nd_05v5 area=4.347e+11p
.ends

Tim Edwards

07/07/2021, 1:17 PM

Would the use of "isosub" solve the issue with the SRAM?

Tim Edwards

07/07/2021, 1:18 PM

@Mitch Bailey: Are you using the open_pdks installation of the standard cell libraries? The "short" model is an old name that was not converted. open_pdks patched that error a long time ago.

Mitch Bailey

07/07/2021, 2:26 PM

@Tim Edwards I might be. I pulled the

openlane

repo

master

branch last month and did

make pdk

there. Looks like my

skywater-pdk

commit db2e067

from February! Sorry for the confusion. What

openlane

tag corresponds to

caravel/develop

Manar Abdelatty

07/07/2021, 2:33 PM

@Mitch Bailey

v0.20

is what I am using now, but I am using

make pdk

from caravel not openlane because caravel has the latest updates to open_pdks

Mitch Bailey

07/07/2021, 2:37 PM

Ok, give me a day or so to get caught up, then I'll report back.

Mitch Bailey

07/08/2021, 6:23 PM

@Tim Edwards @Anmol I rebuilt the pdks using the Makefile from caravel/develop which is

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commit 1a73bd541c6055037261289dd6a88e02bfdae0fe
Date:  Tue Jul 6 23:39:26 2021 -0700

It uses the following

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SKYWATER_COMMIT ?= bb2f842ac8d1b750677ca25bc71fb312859edb82
Date:  Fri Apr 23 19:15:59 2021 -0700
OPEN_PDKS_COMMIT ?= 804f48b18519aa67b1f822bdc352ecbad1c056cb

I don't see this OPEN_PDKS commit on github. The makefile pulls the following commit instead.

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commit 7e29496eecf3ee8e1766f1b7f9441f97204d4735
Date:  Tue May 4 20:33:17 2021 -0400

The current master of

conb

still uses

short

. Is this supposed to be fixed in the open_pdks conversion? https://github.com/efabless/skywater-pdk-libs-sky130_fd_sc_hd/blob/master/cells/conb/sky130_fd_sc_hd__conb_1.spice

Tim Edwards

07/08/2021, 6:58 PM

@Mitch Bailey: The old date of open_pdks suggests to me that maybe you got it from github/efabless and not github/RTimothyEdwards.

Mitch Bailey

07/09/2021, 12:17 AM

@Tim Edwards I found the correct commit for open_pdks and it does appear to change

short

sky130_fd_pr__res_generic_po

. However, it leaves an extra net in the resistor instance. VNB is recognized as the device name instead of sky130_fd_pr__res_generic_po.

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.subckt sky130_fd_sc_hvl__conb_1 VGND VNB VPB VPWR HI LO
R0 HI VPWR VNB sky130_fd_pr__res_generic_po w=510000u l=45000u
R1 VGND LO VNB sky130_fd_pr__res_generic_po w=510000u l=45000u
.ends

See

sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice

Tim Edwards

07/09/2021, 1:55 AM

Hmmm. . . I thought I had a patch for that one, but apparently not.

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