Is there any plans for new IO cells? I started my own IO cell design. I am thinking to just use existing GPIO cell, disable output and implement custom I/O Cell connected to a resistorless ESD-ed pad. This way the GPIO cells don't need to be replaced and the new I/O Cell should help me achieve 100MHz @ 3ns/3ns rise fall time w/ 6pf load. If somebody has some similar projects in works? Is there people who have spare I/O that I can use so I don't have to tapeout just an I/O Cell?

The caravan project has bare pads that you can connect to, although you will need to make your own ESD circuits because they are not present in the bare pads (see the #caravan channel). When we have tested high-speed drivers I would like to make them available integrated into pad layouts. But you will not be able to change the pad layout itself on the harness chip.

"bare pads that you can connect to, although you will need to make your own ESD circuits" My plan is to use the existing top_gpiov2 cell, that integrates everything. But connect custom drivers/receivers to pad_a_noesd_h port of gpiov2 cell. So ESD should be easy. I honestly don't understand: 1. which part of gpiov2 is responsible for what, so I decided to not make any changes to the cell itself. 2. How to properly measure ESD performance. If I can measure it, then I can implement my own GPIO using bare pads If anybody could help me with any of it, it would speed up everything by a lot.

I have a plan to develop a generator for new IO cells, but that work hasn't started yet: