hey all, while running

make user_project_wrapper

I am facing this lvs error, someone help me with this i don`t know why it is connecting

vssd2

it should wired to

vccd1

🙂

What does the layout look like? Is

vssd2

connected to

vccd1

of

user_proj_example

?

i looked in it but can`t find either it is connected or not it is huge 😬

@Tim Edwards Does magic flag a warning for different labels on the same node during extraction?

@Mitch Bailey if you know any way to locate please help me with that 😬 this was mentioned in

cofig.tcl

file:

# disable pdn check nodes becuase it hangs with multiple power domains.
# any issue with pdn connections will be flagged with LVS so it is not a critical check.
set ::env(FP_PDN_CHECK_NODES) 1

I'm thinking that the

ext

files created from magic extraction might have a warning.

don't they need to wrapped in `ifdef USE_POWER_PINS ?

It's wrapped in verilog/rtl/user_project_wrapper.v I showed the snap of the netlist that is generated by openlane in results/lvs/ 🙂

have you checked you have no routing issues?

there came some warning but i am not sure, can u have a look

check the summary report

see 😬

ok, so that looks like it could be a real issue

i had not updated yet as these error were coming

sir i tried with supply pins too same error was coming yesterday 🙂

also you are not defining which pins of the large io/wbs ports are connected to the small ports of your module

yes hardening the example was successfull

then I would suggest going back to the working example, and then add your module in part by part to see when it goes wrong

these are updated modules please correct what all changes r needed 🙂

no way!

so i should run example flow again?? because few hours back I run with these netlist and same lvs error

@Matt Venn, @Mohammad Khalique Khan: If two ports are tied to the same net, then you should either (1) separate the nets with a metal resistor, or (2) use the

ext2spice short resistor

option in magic. Solution (1) requires that both netlists contain the metal resistor device if you want it to pass LVS. For solution (2) magic will make an arbitrary split between the nets by inserting a zero-ohm ideal resistor into the netlist.

netgen

recognizes this method and should handle it correctly.