Hello, anybody could help with a problem related to WB Slave in the user project area where there are slaves in 2 hierarchical levels. I have got write (CPU->mprj) working however I can not read data to the CPU. Kind regards

How are you addressing it in the C program? Are you following the code in

caravel_user_project/verilog/dv/wb_port/wb_port.c

?

HI Tim, thank You for Your response

Revise the solution?

yes

What do you mean by that?

I have solved the problem I have however I am not sure if it is correct, it works but I would like someones opinion as well

I am not the world's best authority on wishbone communication but I'd be glad to take a look at it if you will post the URL to the relevant file in your repository.

ok let me arrange the repo. I think that I have to explain the ide as well. So the problem was that I have 2 registers on the top level status and prescaler mapped to the 0x3000000 and 0x30000004 respectively. Then I have multiples modules named SonarOnChip where I have 15 different registers mapped successively 2-17 in the first instance and 18-33 in the second instance. the problem was to get the data over wishbone to the CPU. Finally I have declared output reg [31:0] wbs_dat_o, as a reg and used "default" section of the case statement in the top level module

I noticed that our example project uses only one register and so does not bother to decode the address, so it's not a particularly good example to follow for a project that needs to decode multiple addresses.

wb_port.c

Your code looks fine to me. Remember that the picoRV32 does not cache instructions, so the instruction fetch time is based on pulling the data one bit at a time from the SPI flash. The SPI flash can be put in DDR quad mode which is 8x the speed (although the flash clock is 2x slower than the core clock, so while you cannot get the instruction fetch time down to one core clock cycle, you can get it down to two for everything except branching instructions).

ok, cool, anyway I will continue testing. I will try the DDR mode as well

Use

reg_spictrl = 0x80780000; // QSPI + DDR + CRM

in your C code to put the SPI flash into QSPI + DDR + CRM mode (the fastest access). Use

caravel/verilog/dv/caravel/mgmt_soc/qspi/

as a guide. In the testbench, the SPI

io2

and

io3

signals need to be connected to

mprj_io[36]

and

mprj_io[37]

, respectively.

ok I will try it out

This vid may help if you are still having issues. I have a repo linked in the description with an example that reads and writes from 2 registers

thank You Matt