@User is the clock speed of the picorv32 is 50MHZ as defined the caravel datasheet?

Yes, the management core was synthesized to a target rate of 50MHz.

How about wishbone interface then? Is there a way to run wishbone interface at clock higher than CPU e.g. 100MHz same as logic or rather wishbone is in CPU clock domain limited to 50MHz and clock crossing for user project should be part of that project?

You can make your own wishbone bus and run it at whatever rate you can get it to synthesize to. However, the current setup is that the management SoC is the wishbone master, so it drives the clock and can only communicate at the same rate as the rest of the CPU. The wishbone does not have a multi-master configuration (although that has been a request and we will consider it for future versions).

Thanks.