Hi All, I’m trying to

make user_project_wrapper

and be stuck at or_pdn step. It just hang the flow then crashed (after 8 hrs?). This issue was reported before and @User suggested to make the macro smaller to get over, but our design cannot be shrunk. Does anyone encounter this issue and/or have an idea how to fix it? Thanks

Placing the following macros:
{'inst_eFPGA_top': ['40000', '40000', 'R0']}
Design name: user_project_wrapper
Placing inst_eFPGA_top
Successfully placed 1 instances
[INFO]: Changing layout from /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/5-ioPlacer.def to /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/5-ioPlacer.macro_placement.def
[WARNING]: Skipping Tap/Decap Insertion.
[INFO]: Power planning the following nets
[INFO]: Power: vccd1 vccd2 vdda1 vdda2
[INFO]: Ground: vssd1 vssd2 vssa1 vssa2
[INFO]: Generating PDN...
[INFO]: current step index: 7
[INFO]: current step index: 8
OpenROAD GITDIR-NOTFOUND 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef at line 973.

[INFO ODB-0223]     Created 13 technology layers
[INFO ODB-0224]     Created 25 technology vias
[INFO ODB-0225]     Created 442 library cells
[INFO ODB-0226] Finished LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
[INFO ODB-0127] Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/5-ioPlacer.macro_placement.def
[INFO ODB-0128] Design: user_project_wrapper
[INFO ODB-0130]     Created 637 pins.
[INFO ODB-0131]     Created 1 components and 224 component-terminals.
[INFO ODB-0133]     Created 652 nets and 222 connections.
[INFO ODB-0134] Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/5-ioPlacer.macro_placement.def
[INFO PDN-0016] Power Delivery Network Generator: Generating PDN
  config: /openlane/scripts/openroad/or_pdn_cfg.tcl
[INFO PDN-0008] Design name is user_project_wrapper.
[INFO PDN-0009] Reading technology data.
[INFO PDN-0011] ****** INFO ******
Type: stdcell, stdcell_grid
    Core Rings
      Layer: met4  -  width: 3.100  spacing: 1.700  core_offset: 14.000 
      Layer: met5  -  width: 3.100  spacing: 1.700  core_offset: 14.000 
    Straps
      Layer: met4  -  width: 3.100  pitch: 180.000  offset: 5.000 
      Layer: met5  -  width: 3.100  pitch: 180.000  offset: 5.000 
    Connect: {met4 met5}
Type: macro, CORE_macro_grid_1
    Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
    Straps
    Connect: {met4_PIN_ver met5}
[INFO PDN-0012] **** END INFO ****
[INFO PDN-0013] Inserting stdcell grid - stdcell_grid.
[INFO PDN-0010] Inserting macro grid for 1 macros.
[INFO PDN-0034]   - grid CORE_macro_grid_1 for instance inst_eFPGA_top
...
[WARNING PSM-0030] VSRC location at (2245.520um, 3230.880um) and size 10.000um, is not located on a power stripe. Moving to closest stripe at (2246.400um, 3255.880um).
[INFO PSM-0031] Number of PDN nodes on net vccd1 = 12067.
[WARNING PSM-0032] Node at (2883600, 3509465) and layer 5 moved from (2872540, 3435880).
...
[WARNING PSM-0032] Node at (189000, 10265) and layer 5 moved from (203450, 1275880).
[WARNING PSM-0032] message limit reached, this message will no longer print
[INFO PSM-0064] Number of voltage sources = 88.

I think that you are placing the macro outside the available area o is bigger than the available are because I see a 4000, 4000 and as far as I know the maximum area is 2950x3500 or something like that

Hi Rodrigo, that’s nm unit, means the offset is 40um. If I disable power connections to the macro (

set ::env(FP_PDN_ENABLE_MACROS_GRID) 0

), it passes the the final step but got lvs mismatches. Below is the layout without power connections to the macro)

Ah ok, sorry. I don't know then what is happening

@User What is the IP size ? Better to place the issue in #openroad channel .. Is your repo available in github ?

@User the IP size is 2840.04 x 3439.78, here is my repo https://github.com/nguyendao-uom/eFPGA_v3_caravel

@User I feel your IP size is too big. My understanding during initial Phase Tool tries to create vertical + horizontal mesh and connect each other which are outside the IP boundary .. You should have atleast 300um free space at each corner allow both vertical and horizontal mesh to meet atleast once.

@User do you know any options to disable that constraint? I know we can disable power connection to the macro then connect manually but that’s not the best option.

I have not much tried much on PDN hacking, You need to try to understand the scripts/openroad/or_pdn_cfg.tcl

So you think there must be vertical + horizontal mesh connected between the power ring and the IP? I don’t see any variable/info define or checking that gap the in the scripts. Can you point to it? Thanks