@User @User Initial my understanding on la_data_in -128 bit signal from mgmt_core can be used as configuration port for design ? But when i review the design, I see on power/default mode these ports are tri-stated until user enable it through software. These floating input towards user_project will create considerable risk - As ports are floating for long duration during power up phase. Not sure real reason for keeping in tri-state mode during power-up phase ? File: mgmt_protect.v /* Project data out from the managment side to the user project */ /* area when the user project is powered down. */ sky130_fd_sc_hd__einvp_8 la_buf [127:0] ( `ifdef USE_POWER_PINS .VPWR(vccd), .VGND(vssd), .VPB(vccd), .VNB(vssd), `endif .Z(la_data_in_core), .A(~la_data_out_mprj), .TE(la_data_out_enable) );

The intended sequence is for the management core to power up first, then in software it will enable the GPIO output that enables the voltage regulators on the development board which power up the user project. So everything will get initialized from the management side while the user project is still powered down. Eventually, I will switch from off-chip voltage regulators to on-chip LDOs, but the sequence will still be the same.

@User As per the waveform review, I see user wishbone reset is removed nearly same time as management core reset. If we are enabling the User power once management core is Up, then user project wrapper will not notice wishbone reset transition- Then user logic itself will not work - which will create much bigger issue. Attached the Waveform capture with caravel setup .. user wishbone reset and mgmt core reset removed neraly same time and LA tri-state removed much latter

@User: I flagged this problem in the issue tracker for caravel, so we'll get it fixed on the next round. For now, my suggestion is that you tie your user project's reset to a "logic analyzer" pin so that you can directly control the reset for your project from the management SoC program, rather than using the wishbone reset. You may want to have a global async reset on the wishbone reset and a more specific synchronous reset on the logic analyzer output.

@User I feel multiple MPW-2/MPW-3/MPW-4 digital project will be impacted due to missing wb_reset transition .. Not sure if this issue shared with rest of the project owners.