Question regarding the Wishbone address range for the user area: Should I decode the complete address (including base address) in my Wishbone slave? Or is it sufficient to just use the lower address bits? In other words: what is the WB address that the userarea slave sees in an access?

for caravel MPW1 it was 0x30xxxxxx

Changes with the new processor are not particularly major and the address ranges are mostly the same as before. The user area is still at 0x30xxxxxx. @User: You can choose to decode however much of that range you want. The user project example doesn't decode at all---it implements one register, and any address in the range 0x30000000 to 0x30ffffff will access the same register (it might go up to 0x3fffffff, but since there isn't enough space on the chip to implement that many registers, I'm not going to go track down that detail).

What happens on the user area WB bus if another address range (0x30000000 to 0x30ffffff) is addressed? Is stb or cyc asserted?

@User: The main things to know about the newest version of Caravel: (1) The PicoRV32 was replaced with a VexRISC created using Litex. The functionality is similar, but the VexRISC implements a debug UART interface, and because we ran out of room, we removed the on-chip multiplier and divider. (2) Everything having to do with the GPIO setup was moved out of the processor and into the housekeeping SPI. Addresses were retained, so that change is largely transparent. The housekeeping SPI got a bunch of additional registers so there's a lot more stuff on the chip that can be accessed from the SPI, such as the I/O configuration and programming. Additionally, stuff like the DLL that was previously only available on the housekeeping SPI is now also internally memory-mapped as well. The only difference in behavior is that when the processor accesses something in the housekeeping module through the memory-mapped interface, the transfer is done byte-wise instead of word-wise, so it takes multiple clock cycles to do that transfer. The housekeeping module stalls the CPU while it does that, so the only effective difference is that reading and writing to, say, the GPIO from management SoC software is a bit slower than it used to be.

@User got it, thanks!