Any idea where to start debugging, when the user_proj compiles fine w/o errors, and when making the user_project_wrapper, the LVS fails with this warning beforehand:

Warning: Ports "vssd2" and "vdda2" are electrically shorted.

I see nothing obvious in the layouts which could cause this fail.

Ahh, the joy of power shorts! I use klayout's trace net command to find shorts. The extract log will show you what circuit you should look at. You can modify klayout's extract layers to start with maybe m5 to m3 (the full layer stack takes too long). And then add more layers until you find it.

I have a suspicion now: The wrapper routs to the IOs right trough the user area. Example: The user macro has a pin on top, with need to connect to IO on the right. Trace runs down (crossing the user area), and then right. I have the suspicion there is something wrong with the blockage of the routes on wrapper level, it should not go through the user macro. What am I doing wrong?

Possibly related to https://github.com/The-OpenROAD-Project/OpenLane/issues/832 and the corresponding fix https://github.com/The-OpenROAD-Project/OpenLane/commit/0d9df0972df385e8b39a0d20f4e9153814df414d

@User Are you on mpw-3a tag for caravel?

I think I know what goes wrong: My macro has vertical M4 power straps, which are different sized and on a different spacing than the wrapper power straps, where also M4 runs vertically through my macro. I guess this eventuelly leads to the shorts in VDD/VSS. Question: Does someone know the correct settings for the PDN of the macro?

Manar Abdelatty would be able to tell you.