does anybody here has an idea what the

reg_la_sample

does? For example what does asserting it to 1 like this

reg_la_sample = 1

will do?

I've found that the best documentation is, unfortunately, the Verilog code itself.

@User: The intent of the

sample

register was to simultaneously capture all of the logic analyzer inputs (on the same clock edge). However, no testbench was written for this, and it looks like it has no useful function because there is no way to read back the value to the management SoC. It needs two fixes, I think, one of which is a self-reset of the

sample

bit (otherwise it is effectively setting

sample

to zero that freezes the captured value, which is a kind of awkward implementation), and the other which is to add a second control bit which will switch the read-back value on the logic analyzer registers between

la_data_in

and

la_data

. I am going to file an issue on github about this.

Yes, using it was causing freezing up in the simulation resulting in timeout.