My flow gets killed consistently at the same point during synthesis. Any idea what could be the reason for this? Following are the final few messages the tool emits before exiting.

....
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000100000 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000001000000 for cells of type $lcu.
No more expansions possible.
<suppressed ~740089 debug messages>

37.22. Executing OPT pass (performing simple optimizations).

37.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
<suppressed ~6927 debug messages>

37.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
<suppressed ~5925 debug messages>
Removed a total of 1975 cells.

37.22.3. Executing OPT_DFF pass (perform DFF optimizations).
[ERROR]: during executing: "yosys -c /openlane/scripts/yosys/synth.tcl -l /home/aanujdu/caravel_tut/caravel_example/openlane/user_proj_example/runs/user_proj_example/logs/synthesis/1-synthesis.log |& tee >&@stdout"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child killed: kill signal

Has anyone faced something similar before and knows a possible fix?

"child killed" might indicate that the out-of-memory supervisor killed it. How much memory do you have on your computer?

That's correct, Tim. I see the following output when I grep for "kill" in /var/log/messages. /var/log/messages:Mar 9 030752 gost kernel: [660942.840913] yosys invoked oom-killer: gfp_mask=0x14200ca(GFP_HIGHUSER_MOVABLE), nodemask=(null), order=0, oom_score_adj=0 / The machine has a 16 GB RAM. Is that an issue?

I would have thought that 16GB would be enough for anything that would fit on Caravel, but memory doesn't necessarily correlate directly with the project size, and you may have had something in your design that is a pathological worst-case for yosys.

I see. So what's the best way to resolve this issue then? Should I synthesize module by module and then eventually get to the full design? Can I find some hints in the synthesis log that can help me figure out what could be this something in my design?

Yeah, probably the only option. Another solution merge the modules together by modifying your RTL

I've had designs where the synthesis ran out of memory that could be solved by using a swapfile (32 GB in my case). This will definitely slow down the synthesis as swapping is expensive, but if your design only needs this much memory occasionally and you have a fast ssd, it can be workable.

Thanks @User. In the second option, you're basically suggesting me to flatten the whole design in just 1 module, right?

@User No, I mean manually simplifying the rtl. For each parametrized cell it is creating uineuq copy of that cell. If you have too much of instances, then it may ran out of memory. Try changing rtl and mergin functionality to make sure that you dont have too many instances

I just noticed the following messages emitted during synthesis:

37.19.15. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $memory\mem[9]$94416 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [7:0], Q = \mem[9] [7:0]).
Adding EN signal on $memory\mem[9]$94416 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [15:8], Q = \mem[9] [15:8]).
Adding EN signal on $memory\mem[9]$94416 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [23:16], Q = \mem[9] [23:16]).
Adding EN signal on $memory\mem[9]$94416 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [31:24], Q = \mem[9] [31:24]).
Adding EN signal on $memory\mem[99]$94596 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [7:0], Q = \mem[99] [7:0]).
Adding EN signal on $memory\mem[99]$94596 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [15:8], Q = \mem[99] [15:8]).
Adding EN signal on $memory\mem[99]$94596 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [23:16], Q = \mem[99] [23:16]).
Adding EN signal on $memory\mem[99]$94596 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [31:24], Q = \mem[99] [31:24]).
Adding EN signal on $memory\mem[999]$96396 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [7:0], Q = \mem[999] [7:0]).
Adding EN signal on $memory\mem[999]$96396 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [15:8], Q = \mem[999] [15:8]).
Adding EN signal on $memory\mem[999]$96396 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [23:16], Q = \mem[999] [23:16]).
Adding EN signal on $memory\mem[999]$96396 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [31:24], Q = \mem[999] [31:24]).
Adding EN signal on $memory\mem[9999]$114396 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [7:0], Q = \mem[9999] [7:0]).
Adding EN signal on $memory\mem[9999]$114396 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [15:8], Q = \mem[9999] [15:8]).
Adding EN signal on $memory\mem[9999]$114396 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [23:16], Q = \mem[9999] [23:16]).
Adding EN signal on $memory\mem[9999]$114396 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [31:24], Q = \mem[9999] [31:24]).
Adding EN signal on $memory\mem[9998]$114394 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [7:0], Q = \mem[9998] [7:0]).
Adding EN signal on $memory\mem[9998]$114394 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [15:8], Q = \mem[9998] [15:8]).
Adding EN signal on $memory\mem[9998]$114394 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [23:16], Q = \mem[9998] [23:16]).
Adding EN signal on $memory\mem[9998]$114394 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [31:24], Q = \mem[9998] [31:24]).
Adding EN signal on $memory\mem[9997]$114392 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [7:0], Q = \mem[9997] [7:0]).
Adding EN signal on $memory\mem[9997]$114392 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [15:8], Q = \mem[9997] [15:8]).
Adding EN signal on $memory\mem[9997]$114392 ($dff) from module $paramod$0b6cc53fd7c219bf00edaf8c0b3e94865ad95aab\bram_wrstrb (D = \data_in [23:16], Q = \mem[9997] [23:16]).

Is yosys trying to synthesize my SRAM? I set the VERILOG_FILES_BLACKBOX variable for that module in config.tcl, so ideally it shouldn't, right?

Modules that are blacboxes need to be empty and marked (*blackbox*k

I see. I did not know this. Then what is the point of setting the BLACKBOX variable in config.tcl?

I said, copy blackbox verilog file. Yes you can do that, it should work