I just got my design (digital) through pre-check succesfully. But there are a couple of things I am concerned about when I check the log files. The first one is a warning:

Warning: Ports "vssd2" and "vdda2" are electrically shorted.

And the second one is the following slack violation on path delay (hold) report_checks -path_delay min (Hold) ============================================================================ Startpoint: la_data_in[6] (input port clocked by wb_clk_i) Endpoint: 3791 (rising edge-triggered flip-flop clocked by wb_clk_i) Path Group: wb_clk_i Path Type: min May I know if any action is needed on these two please?

May I know if any action is needed on these two please?

For first one, you need to debug it to see where it is shorted. Use KLayout to take a look at GDS. "trace net" feature should allow you to find where they are shorted. For second hold time violation, you NEED to fix it, overwise that flip flop will always corrupt data => your circuit will be unusable