More of an architecture question, when setting up an io as

GPIO_MODE_MGMT_STD_OUTPUT

does caravel utilize any user area (user_project_wrapper) for this operation? I am asking to minimize down my debugging issue in GL simulation. If there was something wrong in my design (logically or during the hardening flow), the caravel gatelevel netlist should still initialize the io pad as mgmt right?

The GPIO mode is set by the gpio_control_block in caravel and is programmed through the code running on the SPI flash feeding the management SoC. There are two ways to get it in the correct state: (1) Run a program on the management side that does what I said above, or (2) copy the

user_defines.v

from caravel's

verilog/rtl/

directory to the user project's

verilog/rtl/

directory, and edit the contents. That file customizes part of the caravel base design for your project. It determines the state in which the GPIOs power up, so that they can be in a state usable by your project without programming them from the management side. This is particularly useful if your project wants to start communicating with the outside world immediately on power-up, and not wait for the management to come up first and configure the GPIO. The alternative is to use one of the logic analyzer signals to hold your user project in reset until the GPIO have been properly configured. But with the

user_defines.v

file, you can bypass the management SoC altogether.