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Hi, I am facing some LVS mismatches. Can someone p...
# caravel
a
Hi, I am facing some LVS mismatches. Can someone please help me to comprehend the corresponding log? I am not sure where to start. I am pasting some of the errors that I observe in that log.
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Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__conb_1         |Circuit 2: sky130_fd_sc_hd__conb_1         
-------------------------------------------|-------------------------------------------
VGND                                       |VGND                                       
VNB                                        |VNB                                        
VPB                                        |VPB                                        
VPWR                                       |VPWR                                       
LO                                         |LO                                         
HI                                         |(no matching pin)                          
---------------------------------------------------------------------------------------
My first question is, is this one of the mismatches? I guess that's an automatically added constant value drive cell and in the netlist (after synthesis) I see this cell used to drive only LO bits to all the unused outputs. How do I ensure that the HI port is not causing a mismatch, if it is indeed an issue?
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|                                           
Net: _044_/VPB                             |Net: start                                 
  sky130_fd_sc_hd__conb_1/VPB = 1          |  soc_top/start = 1                        
                                           |                                           
Net: _027_/VPB                             |Net: \mem_word_addr1[11]                   
  sky130_fd_sc_hd__conb_1/VPB = 1          |  soc_top/mem_word_addr1[11] = 1           
                                           |                                           
Net: _060_/VPB                             |Net: \mem_word_addr1[10]                   
  sky130_fd_sc_hd__conb_1/VPB = 1          |  soc_top/mem_word_addr1[10] = 1           
                                           |                                           
Net: _189_/VPB                             |Net: \mem_word_addr1[9]                    
  sky130_fd_sc_hd__conb_1/VPB = 1          |  soc_top/mem_word_addr1[9] = 1            
                                           |                                           
Net: _043_/VPB                             |Net: \mem_word_addr2[11]                   
  sky130_fd_sc_hd__conb_1/VPB = 1          |  soc_top/mem_word_addr2[11] = 1           
                                           |                                           
Net: _112_/VPB                             |Net: \mem_word_addr2[10]                   
  sky130_fd_sc_hd__conb_1/VPB = 1          |  soc_top/mem_word_addr2[10] = 1   

.....

Net: _025_/VPWR                            |Net: \mem_valid1[0]                        
  sky130_fd_sc_hd__conb_1/VPWR = 1         |  sky130_sram_2kbyte_1rw1r_32x512_8/csb0 = 
                                           |  soc_top/mem_valid1[0] = 1                
                                           |                                           
Net: _008_/VPWR                            |Net: \mem_valid2[0]                        
  sky130_fd_sc_hd__conb_1/VPWR = 1         |  sky130_sram_2kbyte_1rw1r_32x512_8/csb1 = 
                                           |  soc_top/mem_valid2[0] = 1                
                                           |                                           
Net: _187_/VPWR                            |Net: \mem_out1[0][31]                      
  sky130_fd_sc_hd__conb_1/VPWR = 1         |  sky130_sram_2kbyte_1rw1r_32x512_8/dout0[ 
                                           |  soc_top/mem_rdata1_0[31] = 1             
                                           |                                           
Net: _110_/VPWR                            |Net: \mem_out1[0][30]                      
  sky130_fd_sc_hd__conb_1/VPWR = 1         |  sky130_sram_2kbyte_1rw1r_32x512_8/dout0[ 
                                           |  soc_top/mem_rdata1_0[30] = 1
Why are the power pins (VPB, VPWR) of sky130_fd_sc_hd__conb_1 cells matched with the data signals of my design? Is this an issue? Seems like it to me.
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Net: top/mem_word_addr1[3]                 |Net: \mem_wdata[15]                        
  sky130_sram_2kbyte_1rw1r_32x512_8/addr0[ |  sky130_sram_2kbyte_1rw1r_32x512_8/din0[1 
  soc_top/mem_word_addr1[3] = 1            |  soc_top/mem_wdata[15] = 1                
                                           |                                           
Net: top/mem_word_addr1[2]                 |Net: \mem_wdata[16]                        
  sky130_sram_2kbyte_1rw1r_32x512_8/addr0[ |  sky130_sram_2kbyte_1rw1r_32x512_8/din0[1 
  soc_top/mem_word_addr1[2] = 1            |  soc_top/mem_wdata[16] = 1                
                                           |                                           
Net: top/mem_word_addr1[1]                 |Net: \mem_wdata[17]                        
  sky130_sram_2kbyte_1rw1r_32x512_8/addr0[ |  sky130_sram_2kbyte_1rw1r_32x512_8/din0[1 
  soc_top/mem_word_addr1[1] = 1            |  soc_top/mem_wdata[17] = 1
Not sure why the address bus signals are matched with the data signals.
t
When using the conb cell, it is often useful to create a verilog black-box entry for it so that you have a model definition with both HI and LO pins. Otherwise, the gate level verilog will declare only the pin that is used, which can lead to LVS issues. That's not your underlying problem, though.
When looking at netgen output, you get side-by-side lists of net partitions. These are nets that have similar fanouts. You should not assume that they are implying that that entry on the left corresponds to the entry directly to its right. Netgen will align the two sides as best it can, but when there are major problems with the LVS, it becomes impossible for it to maintain the ordering and you end up with two lists of basically unordered nets.
The underlying problem here appears to be that the power nets of all the cells (or many of the cells) are disconnected, because all the power pins have a fanout of one (meaning they don't connect to anything else). This can happen if your design doesn't have any fill or decap.
a
1. Thanks a lot, @User, for the elaborate reply. I have not manually instantiated the conb cells, so are you saying I assume that they will be added by default during synthesis and preemptively blackbox them? Indeed, I do not have any fillers or decaps. I'll add them and retry.
t
LVS here is run between SPICE and verilog, and the verilog file does not include the library file of standard cell macros. So the LVS does not see the macro definitions and will create the macros on the fly as it reads instances from the top level verilog file. Since verilog, unlike SPICE, declares pin names as well as the connections to those pins, that's usually a reliable way to get all the module definitions. But because verilog, unlike SPICE, allows unconnected pins to be omitted from the device instance, netgen's automatic generation of the standard cell module definition can be wrong if all the instances it sees of a module are missing a pin. Then it thinks that pin doesn't exist, and that can cause problems with the LVS. However, most likely there will be no problem. If you resolve the issue with the power supplies and you continue to get some error related to the HI and LO outputs of the conb cell, then I can show you how to add a black-box entry for that cell. But probably it won't be necessary.
a
I see. Makes sense. Adding decaps and fillers helped to get rid of the previously seen LVS mismatches, but now I see new ones, related to the taps and fillers. The layout obviously has them now, but the schematic I believe doesn't. Is this expected?
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Instance: sky130_fd_sc_hd__tapvpwrvgnd_1:T |(no matching instance)
  VGND = 23635                             |
  VPWR = 39                                |
                                           |
Instance: sky130_fd_sc_hd__tapvpwrvgnd_1:T |(no matching instance)
  VGND = 23635                             |
  VPWR = 13                                |
                                           |
Instance: sky130_fd_sc_hd__tapvpwrvgnd_1:T |(no matching instance)
  VGND = 23635                             |
  VPWR = 13                                |
                                           |
Instance: sky130_fd_sc_hd__tapvpwrvgnd_1:T |(no matching instance)
  VGND = 23635                             |
  VPWR = 13                                |
                                           |
Instance: sky130_fd_sc_hd__tapvpwrvgnd_1:T |(no matching instance)
  VGND = 23635                             |
  VPWR = 13                                |
                                           |
Instance: sky130_fd_sc_hd__tapvpwrvgnd_1:T |(no matching instance)
  VGND = 23635                             |
  VPWR = 13                                |

......

Instance: sky130_fd_sc_hd__decap_12:FILLER |(no matching instance)
  VGND = 23635                             |
  VNB = 23635                              |
  VPB = 13                                 |
  VPWR = 13                                |
                                           |
Instance: sky130_fd_sc_hd__decap_12:FILLER |(no matching instance)
  VGND = 23635                             |
  VNB = 23635                              |
  VPB = 13                                 |
  VPWR = 13                                |
                                           |
Instance: sky130_fd_sc_hd__decap_12:FILLER |(no matching instance)
  VGND = 23635                             |
  VNB = 23635                              |
  VPB = 13                                 |
  VPWR = 13                                |
                                           |
Instance: sky130_fd_sc_hd__decap_12:FILLER |(no matching instance)
  VGND = 23635                             |
  VNB = 23635                              |
  VPB = 13                                 |
  VPWR = 13                                |
                                           |
That's my config.tcl if it helps.
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set ::env(PDK) "sky130A"
set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/fixed_wrapper_cfgs.tcl
source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/default_wrapper_cfgs.tcl
set script_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) user_project_wrapper
set ::env(RUN_KLAYOUT_XOR) 0
set ::env(RUN_KLAYOUT_DRC) 0
set ::env(MAGIC_DRC_USE_GDS) 0
set ::env(RUN_MAGIC_DRC) 0
set ::env(QUIT_ON_MAGIC_DRC) 0
set ::env(VERILOG_FILES) "\
	$script_dir/../../caravel/verilog/rtl/defines.v \
	$script_dir/../../verilog/rtl/user_project_wrapper.v"

## Clock configurations
set ::env(CLOCK_PORT) "wb_clk_i"
set ::env(CLOCK_NET) "wb_clk_i"

set ::env(CLOCK_PERIOD) "100"

### Macro Placement
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.tcl

### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
	$script_dir/../OpenRAM/sky130_sram_2kbyte_1rw1r_32x512_8.v \
	$script_dir/../../verilog/rtl/soc_top.v"

### user projects gds and lef files
set ::env(EXTRA_LEFS) "\
	$script_dir/../OpenRAM/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
	$script_dir/../lef/soc_top.lef"

set ::env(EXTRA_GDS_FILES) "\
	$script_dir/../OpenRAM/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
	$script_dir/../gds/soc_top.gds"
set ::env(GLB_RT_ALLOW_CONGESTION) "1"
set ::env(ROUTING_CORES) 64
set ::env(FP_PDN_CHECK_NODES) 0
set ::env(PL_RANDOM_GLB_PLACEMENT) 1
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
set ::env(FP_PDN_ENABLE_RAILS) 0
set ::env(DIODE_INSERTION_STRATEGY) 0
set ::env(CLOCK_TREE_SYNTH) 0
Maybe I should enable the FP_PDN_CHECK_NODES and FP_PDN_ENABLE_RAILS flags?
t
You need to set environment variable 
MAGIC_EXT_USE_GDS
(just set it to 
1
) which tells netgen to ignore decap and tap cells, because on the layout side, they resolve connectivity of the power supplies but then get flattened and disappear from the netlist because they don't contain any active devices.
a
Got it. Yeah that did help me to resolve most of the mismatches. I only have two mismatches now, related to the vccd1 of two SRAMs. Is there any way I can open the two circuits that netgen compares during LVS? Do you think that can help?
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---------------------------------------------------------------------------------------
Net: BANK\[3\].RAM/vccd1                   |(no matching net)
  sky130_sram_2kbyte_1rw1r_32x512_8/vccd1  |
                                           |
Net: BANK\[4\].RAM/vccd1                   |(no matching net)
  sky130_sram_2kbyte_1rw1r_32x512_8/vccd1  |
---------------------------------------------------------------------------------------
t
BANK\[3\].RAM
and 
BANK\[4\].RAM
are two different SRAMs? The LVS is suggesting that both of them have their power supplies disconnected.
a
Thanks, Tim.
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