@User @User @User I will be glad if I can get the insight behind the testbenches in caravel. There has been a weird behavior of XXXs propagating in the caravel during GL simulation of OpenRAM project. I am not able to understand the purpose of setting different registers and io pads in the testbenches of the caravel_user_project: 1. What’s the difference between these two lines: https://github.com/efabless/caravel_user_project/blob/main/verilog/dv/io_ports/io_ports_tb.v#L34-L35 2. Why is

reg_spi_enable = 1;

commented out here: https://github.com/efabless/caravel_user_project/blob/main/verilog/dv/io_ports/io_ports.c#L49 3. Why do we need to disable debug mode in the la_test: https://github.com/efabless/caravel_user_project/blob/main/verilog/dv/la_test1/la_test1_tb.v#L104 whereas it is not required in the io_ports test. 4. Why are we enabling/disabling

CSB

in the testbench: https://github.com/efabless/caravel_user_project/blob/main/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v#L79-L86 when that is just a reg and is not being passed anywhere to the dut? There are a lot of ambiguities with the current dv setup and I will appreciate some documentation (atleast comments behind the motive) or a reply to this thread so I can send a PR for documentation.

The chip top level is sensitive to the input CSB (GPIO 3) because it feeds into part of the reset network for the chip, even though it does not control the reset state directly. Since MPW-4, the housekeeping SPI can be disabled so that the externally applied value to CSB no longer has any effect, but in simulation it still has to be applied from power-up until the SPI is disabled. Then it can be disconnected. It's a little tricky to set this up in simulation if you want to use GPIO 3 as a user project input. The way that I found works is to let CSB be a separate register with value 1 or 0, and use the value of CSB to set mprj_io[3] to either 1 or Z. Some of these settings (like CSB and debug mode) are just "boilerplate" and copied from testbench to testbench without regard to whether they have any function within a particular testbench.

@User “Some of these settings (like CSB and debug mode) are just “boilerplate” and copied from testbench to testbench without regard to whether they have any function within a particular testbench.” They are not copied from testbench to testbench which is why I cannot figure out the intention.