Hi, is it possible to store the data into the memory in management area of caravel and then retrieve those data into the module in userspace? If so how is the addressing of mgmt area memory is done? Any help

That's not possible without a wishbone multi-master, which I think the current version of the VexRISC does not support, although you would need to check with Mohamed Shalan about what's specifically supported by the VexRISC. I think that what people have been doing who need this capability is to add an SRAM block into the user design, and memory map it on the wishbone bus so that the management SoC can write to it; and then the user project can read from the SRAM 2nd read-only port. In theory, we could do this with the management SoC SRAM, which exports the read-only port wires to the housekeeping module, by defining a mode in which the housekeeping redirects those wires to the user project wrapper, and then defining pins for them in the user project wrapper. But that hasn't been done.

@User: Note that what was suggested here (as I understand it) was to write into RAM from the management SoC and read from the user project, which is a simpler case than what you pointed to in the Google docs. Since we are using dual-port SRAMs from the OpenRAM macro library, there is already the capability for a 2nd process to access SRAM data in read-only mode. The only thing lacking is that there is no wiring from the 2nd read port to the user project. So it would be trivial to implement with barely any additional overhead.

yes, mine is more complex because it allows multiple user projects access to the memory

How to load data into mgmt SoC RAM externally once the chip is fabricated. From responses I understand that I can wire specific location of memory created in user space to specific locations of mgmt SoC memory via wishbone? @Tim Edwards @Matt Venn

you could have some data in flash that the firmware can read and then write over wishbone to your project