I'm trying to get past the consistency checks in the precheck but am probably overlooking something here. I'm getting this:

{{WARNING}} Consistency Checks Failed+ Reason: Pins check failed. The user is using different pins: la_data_in[94], wbs_adr_i[29], la_data_out[18], wbs_dat_i[15],

..and many, many more pins are listed The info.yml path seems to point to this gate level Verilog, which I have replaced with the one openlane has generated for my design: https://github.com/dan-rodrigues/caravel-vdp-lite/blob/vdp-lite-custom-diode-script/verilog/gl/user_project_wrapper.v I also noticed I don't get a

_.powered.v

as I did for my user project, which is contained in the wrapper and inserted as a macro. Has anyone passed this check with their own design and can point to anything obvious I've done wrong here?

You need to have a

caravel.synthesis.v

under your verilog/gl and point to it in your info.yaml. Check https://github.com/efabless/caravel/tree/develop