open-source-silicon.dev

I have runs/user_project_wrapper/results/synthesis/user_project_wrapper.synthesis.v, but it's basically just a couple  of module definitions

<@U0172QZ342D> the `verilog/gl` directory looks like it's for the gate level verilog. You should be able to find your version at `results/lvs/user_project_wrapper.lvs.powered.v` I believe.

Probably want to put the gate level verilog for the modules there, too.

there is only that single .v file in the runs directory

and I don't beleive there should be a gate level netlist because there aren't meant to be any gates in user_project_wrapper, just wires

<@U0172QZ342D>: It's not necessarily a single gate/a couple of gates for all users. However, I would like to capture "an elaborated verilog". So, it would be better to overwrite it with that even if it's a single gate.