Hi, ```[10/28/21 06:10:29 PDT] FAILURE ...
# shuttle-precheck
z
Hi,
Copy code
[10/28/21 06:10:29 PDT] FAILURE
            2 Check(s) Failed: ['Klayout BEOL', 'Klayout Pin Label Purposes Overlapping Drawing'] !!!
Getting these errors while running pre-check job. Can someone please help me with this? What does it mean? Thread in #shuttle
m
@User Just a guess, but check your layer purpose pairs. You may be using a layer that is supposed to be a pin label as a drawing layer. I believe pin layers should always be enclosed by pin drawing. It may also be that your pin label origin is not over the appropriate drawing pin or drawing layer.
@User Did you resolve this? There should be more details in one of your DRC logs.
z
Ah thank you so much Mitch for your reply, @User, @User can you please follow up with this error?
w
Ummm... Are you saying that the pins should be on
pin label layer
but in our case for some reason they are at
metal drawing layer
? @User
@User Any details in DRC log?
And what is
layer purpose pairs
m
@User From what I heard, there were some designs that had `pin layer`s without
drawing
layers. LVS considered them to be the same layer, but `pin layer`s were not used in the actual masks. I believe the DRC rule is that `pin layer`s must be enclosed be the
drawing
layer. There may also be a rule for `pin label`s whose origin is not inside a
pin
layer. There should be a log file with the error markers.
layer purpose pair
is Cadence virtuoso terminology that roughly corresponds to GDS
layer number
and
data type
. In klayout, you can see it as a number in the form of
8/50
after the layer name.
w
ok so if I understand this correctly, the IOs should have both
pin layer
as well as
drawing layer
I can see both the layers as you have mentioned
There is pin layer enclosed by drawing layer
m
@User thanks for the picture. Can you change the color of
met2.pin
? It would make it easier to visually check. Is the origin of
analog_io[17]
inside
met3.pin
or on the border? Did you locate the error flag file to find the exact error location?
w
Is it better, I am color blind so these colors work differently for me
I would look at the log file and see if there are any coordinates mentioned in there
m
To me, it looks like the pin for
io_oeb[23]
is missing
met2.drawing
. Can you send a screen shot with
met2.pin
off?
w
io_oeb[23]
is fine I would have to look at other pins
m
Does the DRC report give you any coordinates?
w
I am shared this snippet from my other team member responsible for submission process. I would have a meeting to go through the log file in detail to see if there are any information. At least this snippet proves that the error is what you mentioned,
pin layer and drawing layer
Hopefully I would find the relevant coordinates otherwise its gonna be really tedious going through it pin by pin
m
@User How about
precheck_results/<timestamp>/out_pin_label_purposes_overlapping_drawing_check.xml
w
I am browsing through it atm
m
@User I think you can load this into klayout. Tools->Marker Browser
w
I have been looking at the wrong IOs, the problem is not with the IOs of wrapper but with the IOs of macro.
There is only
pin layer
, no drawing layer
I had generated this through innovus, any idea how I would make sure it uses drawing layer ? In innovus I only see met2 layer, and not any
pin layer
or
drawing layer
m
Sorry, I don't know anything about innovus.
w
oh a pity, nevertheless, thanks for your patience and the help.
z
Thanks @User.
w
Though I still have a question why is there a pin layer in the first place if it does not have any actual mask? Having the drawing layer would not suffice?
m
May have something to do with LEF generation.
Also, pin layers are used to differentiate between ports and named nets.