Hey, any idea on how to solve this? @User

Looks like your ports don't match the golden wrapper ports. You may be missing vccd2, vdda2, vssa2. Try adding those to your

verilog/gl/user_analog_project_wrapper.v

.

Ohh ok i will try that

Did you tie the user1 and user2 power supplies together? That might explain why the ports vccd2, vdda2, and vssa2 are mismatching.

@User Yes tied them, dont i do that?

vdda is 3.3v, vccd is 1.8v

Hey @User, yes I know that...so in the pad frame you have VCCD1 VCCD2 -1.8V and VDDA1 VDDA2 - 3.3V , VSSA1 VSSA2 -GND .... so i connected all the same voltage source and the GNDs

I believe the vccd1 and vccd2 regulators are unique as are the vdda1 and vdda2 regulators. I don't know of any reason to tie 1 and 2 together.

Ok so what about GND?

Normally, the vss* nets are physically connected through the substrate and on the pad frame external to the chip. I believe the vss* nets in the netlist are separated to limit the effect of noise on unrelated power domains. If the

user_project_wrapper

has them separate, I know of no reason to short them.

So which means I should not tie any of the power rails, and use any of them as supply according to voltage and then connect the cells in any VSS* GNDs irrespective of which voltage pin i used for its supply?

Ideally, I believe vssa1 is intended to be used with vdda1, etc. However, in actual practice, I don't know that it makes much difference if you are only using one power supply.

Ok thanks Mitch, @User 1. Are the GND pins VSS* connected themselves in the pad so that i can use any VSS* for GND and not tie all of them together 2. So the below image has the power rails with its respective GND pins i guess....so for example if i connect a cell with vdda1 then should i just need to connect vssa1 to the cell, and likewise for all (like for VCCD1- VSSD1)..and no need to tie these GNDs? Note: I use all the power pins (both 1.8, 3.3 - *d1,2, *a1,2)to supply power all around the chip

You can use any VSS for ground, but some are "soft tied" through the substrate. Ideally if you power your project off of

vccd1

then your ground return should be

vssd1

, and likewise for

vccd2/vssd2

and

vdda1/vssa1

and

vdda2/vssa2

(3.3V domains). Within the user project, the grounds may be tied together if you want, and also the 1.8V supplies can be tied together and the 3.3V supplies can be tied together. However, if you do that, you will need to put a "metal resistor" spanning the width of the power suppy line, close to the supply pin connection, so that the specific supply line pin name remains on an isolated net. Otherwise, the nets get merged, and some of the pins get removed because there can only be one name for a net, and then you end up with a precheck error..

Thanks Tim I got that!