Hi, Has anyone encountered this weird FEOL DRC fro...
# shuttle-precheck
n
Hi, Has anyone encountered this weird FEOL DRC from the precheck? This was not reported from the magic? @User any suggestions? Thanks
t
That is weird, and please report it. When klayout shows a false positive DRC error, I have no recommendations for workarounds.
n
Thanks @User I will check again on the efabless portal then report it
a
Does not look like you are viewing correct region. Could you please zoom to error's location in question?
m
Haven't used klayout for DRC checks too often, but it looks like the error is at (5.06, 355.979) in the
DSP
cell. Your screenshot is showing (1355.44, 656,621) of
user_project_wrapper
. Is this the same location? Looks very small so you might have to zoom in a bit. (0.001, ?).
n
I think the coordinate of the errors corresponding with the DSP block is top. The showing in the screenshot (bottom right) is for user_project_wrapper top
That’s why there is only 6 errors counted under DSP block, the user_project_wrapper has 6x DSP blocks
Hi @User I can confirm that the DRC from the SRAM cell now disappear on efabless portal precheck, but I see another weird DRC (pls. see above screenshots). The precheck results from local and efabless portal are the same (6 nds.1 errors flagged in the DSP block). This is my repo: https://github.com/nguyendao-uom/open_eFPGA.git
m
@User Thanks for the response. Can you zoom in really close (like 0.02um scale instead of 500um) on the error?
o
@User thanks for the response, I will raise visibility on your issues but it seems that the precheck is now behaving consistently locally and on the platform cc: @User
n
image.png,image.png
m
@User Are you sure your repo's up-to-date? The
user_project_wrapper.gds
in the repo doesn't look like your screenshot.
n
yes, it does. This is on efabless portal
image.png
m
I don't have access to the efabless data. I was looking at the github repo you posted.
n
Thanks @User, you should get the same gds as shown on efabless?
m
Sorry, I was looking at some other chip, I guess. I can see it now.
The
decap_12
label is on the nsdm drawing layer. Can you move it to text/drawing (83/44). There are also VGND and VNB labels on the nsdm layer. The VGND label should be on layer met1/label (68/5) and the VNB label should be on pwel/label (64/59). You could change these label layers and retry. @User This is the
sky130_ef_sc_hd__decap___12
cell.
n
@User I don’t think I should change the std/ef_cell. But yes, this error seems only appear with sky130_ef_sc_hd__decap_12 placing at the edge.
t
@User: The "ef" version of the cell was made by direct manipulation of the GDS file to remove a few contacts and change the perimeter of the local interconnect layer. So there should be no difference in labels and how they are attached between the "fd" and "ef" versions (noting that, of course, "should be" and "is" are two different things).
j
@User did you manage to solve the nds/psd issues?
m
I reported this 'error' with
sky130_ef_sc_hd__decap_12
back in November and I thought @User fixed it. @User how old is your pdk?
n
I have no idea why it flags that error, does not look like the min nsdm width < 0.38um
t
@User (@User): Yes, I agree, this sounds exactly like the issue you reported and which I fixed in open_pdks version 1.0.240 on November 16.
Copy code
posted: November 16, 2021 at 3:00am     version: 1.0     revision: 240
...
Also: Corrected the sky130_ef_sc_hd__decap_12.gds file, which had incorrect label layers, causing issues with LVS when read into magic, even though the mask layout was valid.
@User: It flags the error because the label was put on a non-text layer, which the rule deck doesn't expect. But as noted above, that was fixed last year.
n
Thanks @User @User So, I guess I’m using the old version. Except the label, is there any changes? If not, I can just replace the cell only without re-run the full flow?
t
To my knowledge, yes, you should be able to do a simple cell replacement.
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