I look forward to more substantial proofs of concept here - an ALU is obviously a lot more convincing than a lot of buffers chained together :)

Well, implementing an ALU in reversible adiabatic pipelines is straightforward; Carlin Vieri did that already for the SCRL logic family in the Pendulum chip at MIT back in 1999 (see his dissertation) and Ressler did one using Fredkin gates way back in the late 1970s. Granted, however, there is lots of work that still could be done in terms of optimizing a reversible ALU for minimum energy/area/whatever in a particular process. However, even in standard irreversible CMOS, even just optimizing an integer adder is not straightforward at all--there is an enormous amount of research on different adder designs. So, it all depends on how much someone is willing to spend to try to optimize the design.