Got a newbie question here: What's the concept beh...
# open_pdks
m
Got a newbie question here: What's the concept behind the definition of a
max_transition
parameter in the liberty files, and what happens if I get max slew violations for exceeding that time?
t
This is more of a question for #openlane, but anyway,
max_transition
tells the synthesis tools to keep the transition time (time for the output to rise from logic 0 to logic 1 or to fall from logic 1 to logic 0) inside of the specified limit. That will prevent the tools from synthesizing something with a huge fanout with a load that's slow to ramp up or down.
m
Thanks! That would normally translate into other timing violations? I was asking because running the new timing scripts on the old MPW-2 GDS gave me max slews violations but no hold or setup violations, and I didn't know if there were other reasons I shouldn't exceed the max transition (I read there might be some power issues if they are too slow)
t
It's possible that if you have a large fanout on a net and the
max_transition
is too short, that the buffering you need on the net would cause the same setup violations that you'd get by having a slow signal transistion. Generally speaking, though, you want to keep clock edges sharp, since slow transistions can cause metastbility problems as well as an increase in power consumption.
m
Thanks!