@User how would you recommend the best way to characterise an on chip inductor? I know you mentioned before increasing the bias current till the oscillator starts. But what would be the best way of testing just the inductor itself? Or we should still use an oscillator as a piece of test equipment essentially?

Measuring just the inductor by itself can be done with a good vector network analyzer and with a layout that includes a set of ground-signal-ground pads and a probe (e.g. from Cascade Microtech) for each terminal of the inductor. You also need calibration structures (e.g. open, short, known resistor) to de-embed the effects of the probes and pads and the coupling between the probes at that particular spacing. If there is wiring between the probe pad and the inductor terminal then de-embedding structures are needed for that too, though that might not work perfectly if there is mutual inductance between the wiring and the inductor itself. The probe contact resistance needs to be very repeatable for the de-embedding to work, and then you get s-parameters for the inductor, with any magnetic effects due to that particular layout. (e.g. If there is a ring of metal around the inductor for the grounds of the GSG probes, then that will reduce its inductance due to the shorted turn. You would want the same ring to be present in your product layout for the model to be valid for that product.) Also we would need to get a die without the redistribution layer polyimide, (or remove it) in order to probe. In my opinion, even with serious equipment and effort, any discrepancy between field solvers and the measured result would most likely be more due to measurement uncertainty than poor simulation or non-ideal fabrication of layer thicknesses etc. When I worked for a company where we did have the equipment to do those measurements, we gave up on doing it that way. The nice thing about the oscillator measurement is that you can do it with any spectrum analyzer (maybe even frequency counter) and a multimeter, and the overall tank Q estimate should be pretty good provided you know the relationship between gm and Id for the fets in the oscillator. It will include the losses of the capacitors and wiring in the tank circuit, so that layout needs to be good and it may not be possible to apportion the losses perfectly between the inductor and other components.

Sorry for such a late reply to this. Thanks for the very useful information. I certainly don't have access to microwave probing machines and it seems clear there's a whole load of overhead for not clear results. In that case I think the oscillator is clearly the way to go. I will look into this further and see what I can pull together before the tapeout which is starting to loom ahead of us Thanks again!

@Chris Jones Are these the kind of de-embedding structures you were talking about?

Sorry I was away. Yes that is the sort of thing. I don't recall how to deal with the thru properly since it is not zero length nor zero loss, and I have no idea what impedance it is supposed to be. Most on-chip VCOs need centre-tapped differental inductors rather than single-ended like this one, but perhaps no more VNA ports are needed to measure these, if we stipulate that the centre tap must be grounded (it is usually at AC ground (VDD) anyway when used in a real circuit). I'm not sure whether they have a complete ring of ground around the inductor, but if they do then that will significantly reduce the inductance, and if they don't then I question how their probes measure with respect to the same reference. If the ground loop is only completed when the probes all touch down then the short standard is not like the one with the inductor. It just seems too hard to me. By the way, I had a habit of deliberately inserting a very thick closed metal ring around each inductor, the ring being about twice the diameter of the inductor itself. Currents get induced in the ring so I made it thick to reduce the loss, and included it in the Fasthenry geometry. It does reduce the inductance and can reduce the Q slightly, but by a well-controlled and modelled amount, and it makes coupling to other parts of the chip roughly 6dB better (half the induced voltage), and it reminds layout people to keep other people's crap away from the inductor. If other people put e.g. logic traces instead of where the ring went (which used to happen otherwise), it would still alter the inductance and so VCO frequency, but instead it would be dependent on the state of the logic lines (since drivers and inputs have different RF impedance depending on state) which was worse than a constant shift, as well as directly carrying interfering signals from the logic into the VCO.