open-source-silicon.dev

<@U016HSALFAN> I ran CVC on the `APU` design and got the following 'errors' (which may be classified as warnings, if there is no problem.)
```DmaAddr[15] shorted to VPWR
DOUT[5] shorted to VGND```
The data I'm using is from <@U01634FSETZ>. `develop-cvc` branch, I believe. I checked the `lvs/APU.lvs.powered.v` file and indeed, these 2 nets were connected to power/ground.
I was wondering if this is the intended operation of the circuit? If it is, I can ignore these errors for this circuit.

There are 8 other designs (only 2 of which have LVS errors) with the same type of error. I can create a list of terminals tied to power/ground. Would that be useful.

Looking at the verilog, it appears that these 2 signals are indeed tied to the respective power signals.