@User Good news is that with magic 8.3.132, DFFRAM LVS completes with no errors. Bad news is that the parent cell, mgmt_core, is now extracted with a split power net. VPWR &

_65235_/VPB

Here's a snippet of the extracted spice. Before (8.3.125?)

XFILLER_175_4508 VGND VPWR VPWR VGND sky130_fd_sc_hd__decap_4
X_65235_ VGND VPWR _65235_/D _65235_/CLK la_output[55] VGND VPWR sky130_fd_sc_hd__dfxtp_4

After (8.3.132)

XFILLER_175_4508 VGND VPWR VPWR VGND sky130_fd_sc_hd__decap_4
X_65235_ VGND _65235_/VPB _65235_/D _65235_/CLK la_output[55] VGND _65235_/VPB sky130_fd_sc_hd__dfxtp_4

If you want to run the test in

caravel/openlane

, first add the following lines to

mgmt_core/config.tcl

set ::env(LVS_EXTRA_GATE_LEVEL_VERILOG) "
    $script_dir/../../verilog/gl/DFFRAM.v
    $script_dir/../../verilog/gl/digital_pll.v"

And then

gunzip ../gds/mgmt_core.gds.gz
flow.tcl -design mgmt_core -tag ext_test -lvs -gds ../gds/mgmt_core.gds -net ../verilog/gl/mgmt_core.v

@Mitch Bailey: But before, when you applied the manual awk renames, this didn't occur, right?

@Ahmed Ghazy Correct. With magic 8.3.125(?), I extracted mgmt_core, fixed DFFRAM, and got a clean LVS. With magic 8.3.132, I extracted mgmt_core and the top VPWR net was split in two. (But DFFRAM was ok without changes)