@User they are reversed compared to what? oh you mean at the caravel level. The address and bits would not matter, but the wen would... 2. I did flatten this to fix some implant/well spacing issues. I'm not sure about all of the other changes...

In the storage block, I'm getting the following correspondence.

mgmt_addr[0:7] mgmt_addr[7:0]
mgmt_rdata[0:31] mgmt_rdata[31:0]
mgmt_rdata[32:63] mgmt_rdata[63:32]
mgmt_rdata_ro[0:31] mgmt_rdata_ro[31:0]
mgmt_wdata[0:31] mgmt_wdata[31:0]
mgmt_wen_mask[0:3] mgmt_wen_mask[3:0]
mgmt_wen_mask[4:7] mgmt_wen_mask[7:4]

Sorry, wasn't the

wen

bus, but the

mgmt_wen_mask

bus.

ah, that would be right then

@Matthew Guthaus: What would cause this though? Does that mean that the labels on the SRAM pins are reversed?

@Ahmed Ghazy Some of the subcells "matched" with unmatched or undefined pins. This may have resulted in circuits with symmetry being matched in reverse and then propagating all the way to the top. I also noticed that the sram subcells had labeled text, but not defined ports (no port statements in the .ext files). Don't know if that has an effect or not. I'll double check both later. Other subcells had to be flattened in netgen all the way to the top. In the flattened state, it's possible that the symmetry reemerged. @Tim Edwards Is there anyway to force correspondence at the ports?

@Mitch Bailey: If you want to force correspondence at the ports, then the labels need to be declared as ports. There is still an investigation that I need to do about how SkyWater thinks pins are supposed to be represented, because there is some kind of disconnect there which means that various tools are seeing plain text instead of pins or vice versa. One "quick fix" solution is cell annotation: If you have read in a cell from GDS, you can read in either a LEF macro or SPICE netlist afterward, and it will make sure that the pin names match between the two, including handling case-sensitivity differences, port order (for SPICE), and port locations (for LEF). It does not do anything to the underlying geometry, so it is not "cheating" to use the netlist you're running against the layout in LVS to annotate the layout.

@Tim Edwards Thanks! Any examples of cell annotation in the openlane flow?

Mainly it would just be

gds read _<file>_ ; lef read _<file>_

or

gds read _<file>_ ; readspice _<file>_

.

I believe the sram pins are correct but they are flipped when connected. Is it a MSB/LSB issue in verilog? I notice that Mitch wrote [0:31] rather than [31:0] @Ahmed Ghazy

@Matthew Guthaus The pin correspondence list output from LVS is flattened. I put it in bus format to hopefully make it easier to see the differences. The left and right side could just as well have been reversed.

@Mitch Bailey yes, I meant to be referring to what @Ahmed Ghazy may have put in the verilog