@User Previously, I believe you mentioned that magic occasionally had problems extracting large layouts because the partitioning algorithm wouldn't detected connected nets across partitions. I'm using 8.3.179, but I think I've come across that same problem. I'm doing device level LVS on the

storage

macro from mpw-2 caravel. The netlist has

p_en_bar0

connecting

control_logic_rw

and

bank

in

sram_1rw1r_32_256_8_sky130

. Here is a snippet from the spice.

.SUBCKT sram_1rw1r_32_256_8_sky130 ...
...
Xbank0 ... p_en_bar0 ... bank
Xcontrol0 ... p_en_bar0 ... control_logic_rw

And here is the extracted netlist.

.subckt pk_pk_sram_1rw1r_32_256_8_sky130 ...
Xpk_control_logic_rw_0 ... pk_control_logic_rw_0/p_en_bar ... pk_control_logic_rw
Xpk_bank_0 ... pk_bank_0/p_en_bar0 ... pk_bank

Looking at the layout, the 2 blocks appear connected. Left side is

control_logic_rw

and right side is

bank

. There may also be some problems with the vdd connections to the bit cells. If you think it may be a real problem, I can log the issue to magic with the setup I'm using. @User Just so you're aware.

I'm not sure how this can be. They passed LVS with Calibre.

@Matthew Guthaus What I'm saying is that this is appears to be a magic problem. I just thought you might want to be aware of it.

@Mitch Bailey Thanks. Yes, I think I've sorted through all these in the newer versions