@User Just a heads up on where I'm at on the device level LVS of the

storage

module for the mpw2 caravel. (netgen 1.5.196) The device counts match, but the net counts are way off.

Subcircuit summary:
Circuit 1: storage                         |Circuit 2: storage
-------------------------------------------|-------------------------------------------
...
Number of devices: 22399                   |Number of devices: 22399
Number of nets: 4479 **Mismatch**          |Number of nets: 39319 **Mismatch**
---------------------------------------------------------------------------------------

The problem appears to be related to unmatched floating pins in subckt definitions. For example, VSUBS pin is extracted in a hierarchy of cells that only contain pmos devices, namely the precharge array. The corresponding extracted layout is

.subckt pmos_m1_w0_550_sli_dli D S G w_n59_n29# VSUBS
X0 D G S w_n59_n29# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
.ends

.subckt precharge_1 bl br en_bar vdd VSUBS
Xpmos_m1_w0_550_sli_dli_0 br vdd en_bar vdd VSUBS pmos_m1_w0_550_sli_dli
Xpmos_m1_w0_550_sli_dli_1 vdd bl en_bar vdd VSUBS pmos_m1_w0_550_sli_dli
Xpmos_m1_w0_550_sli_dli_2 br bl en_bar vdd VSUBS pmos_m1_w0_550_sli_dli
.ends

The

pmos_m1_w0_550_sli_dli

is flattened as an unmatched subcell and VSUBS is floating. The schematic spice doesn't have the VSUB terminal,

.SUBCKT precharge_0 bl br en_bar vdd
* OUTPUT: bl 
* OUTPUT: br 
* INPUT : en_bar 
* POWER : vdd 
Xlower_pmos bl en_bar br vdd sky130_fd_pr__pfet_01v8 m=1 w=0.55 l=0.15 pd=1.40 ps=1.40 as=0.21u ad=0.21u mult=1
Xupper_pmos1 bl en_bar vdd vdd sky130_fd_pr__pfet_01v8 m=1 w=0.55 l=0.15 pd=1.40 ps=1.40 as=0.21u ad=0.21u mult=1
Xupper_pmos2 br en_bar vdd vdd sky130_fd_pr__pfet_01v8 m=1 w=0.55 l=0.15 pd=1.40 ps=1.40 as=0.21u ad=0.21u mult=1
.ENDS precharge_0

so it gets a proxyVSUBS terminal attached.

Subcircuit pins:
Circuit 1: precharge_1                     |Circuit 2: precharge_1
-------------------------------------------|-------------------------------------------
en_bar                                     |en_bar
vdd                                        |vdd
bl                                         |bl
br                                         |br
VSUBS                                      |(no matching pin)
---------------------------------------------------------------------------------------

The next higher level of the hierarchy yields

Circuit 1: precharge_array_0               |Circuit 2: precharge_array_0
-------------------------------------------|-------------------------------------------
precharge_1 (65)                           |precharge_1 (65)
Number of devices: 65                      |Number of devices: 65
Number of nets: 133 **Mismatch**           |Number of nets: 197 **Mismatch**
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: precharge_array_0               |Circuit 2: precharge_array_0

---------------------------------------------------------------------------------------
Net: VSUBS                                 |Net: dummy_133
  precharge_1/VSUBS = 65                   |  precharge_1/proxyVSUBS = 1
                                           |
(no matching net)                          |Net: dummy_134
                                           |  precharge_1/proxyVSUBS = 1
                                           |
(no matching net)                          |Net: dummy_135
                                           |  precharge_1/proxyVSUBS = 1

The VSUBS in the layout eventually connects to VGND, but the dummy pins created on the schematic side remain and are counted as unmatched. I have a work around by flattening certain cells. I'll log an issue to netgen's github once I've tested the sample data. Sorry, but it's not a minimal case.

Some (maybe all) of this is due to magic insisting on a substrate connection for all cells. I am working on a better substrate extraction method---I had it almost working but then got called off on various other emergencies and have not been able to get back to working on it yet---which should solve the problem above, because magic won't extract a substrate connection on cells which have no connection to the substrate other than the fact that it happens to exist below the circuit. This happens for all circuits completely in an nwell or deep nwell.