@User Hopefully, you can clarify some of magic's extraction rules. In the GDS for the

chip_io

block, I'm flattening all the subcells for

sky130_ef_io__vssio_hvc_clamped_pad

with

gds flatglob

before extracting. Looking at the layout, it seems to me that

VSSIO

is shorted to

VSSIO_Q

, but there is no message in the extraction log.

VSSIO_Q

is missing from the spice file. The layout has labels on

met5/label (72/5)

and rectangles and labels on

met5/pin (72/16)

. The

ext

file has both

VSSIO

and

VSSIO_Q

ports that are merged but not directly. There are several intermediate nodes. Is this why there is no warning message? Also, how are the labels and pins extracted? Are labels from both the

pin

and the

label

layers valid? Will a

met5/label

on a

met5/pin

give a valid port?

Yes, it appears that all the code I added relative to checking for conflicting port names depends on both ports being connected together in the same layout cell. In that case, there is an

equiv

statement in the .ext file. If they are connected through hierarchy, then they are part of a series of

merge

statements. I am looking at how to get those cases to be handled in the same way.