I see an LVS error: devices and pins mismatch. Also, flow failed due to warnings related to power. Attached is the snapshot of the error. Please someone help.

@User Can you post the

31-lef.log

file?

Sure. Here it is!

There are too many things wrong here to know what's the root cause. There is nothing in either netlist except for decap, fill, and tap cells (no logic at all). The tap and fill cells are showing up in the circuit summary, so something is wrong with the setup file, which should be forcing those cells to be ignored. Cells in circuit 2 are being parallel merged (which is correct behavior) while cells in circuit 1 are not (either a setup issue or a netlist issue).

Thank you very much, @User, I will make sure to check the setup and netlist and get back if I need more help.

@User There's the

user_proj_example

which contains all the logic. Normally,

user_project_wrapper

doesn't contain fillers, right? @User There many be problem with your power connections. The schematic side has all the filler cells reduced to 1 device, but on the layout side , they appear to be disconnected. You might want to check your

user_project_wrapper/config.tcl

against the sample.

Okay. Thanks, @User. I will try to figure out the issues in config.tcl. I will get back if I need more help.